The Signal and Power Integrity Engineer at Google will be part of a team focused on developing custom silicon solutions for Google's direct-to-consumer products. This role involves working on chip package design with signal and power integrity simulation at the chip, package, and system levels. The engineer will collaborate with system architects, ASIC engineers, and other teams to drive chip packaging signal and power implementations. The position emphasizes innovation and efficiency in hardware experiences that impact millions of users worldwide.

• Bachelor's degree in Mechanical Engineering, Material Engineering, Electrical Engineering, Technology, Science, or a related field, or equivalent practical experience.
• 8 years of experience in SI/PI design for chip/package or system PCB.
• Experience in industry SI/PI modeling tool chains such as HFSS, ADS, Sigrity, and Siwave.

• Drive SI/PI analysis and optimization for HPC based on 2.5D/3D technology.
• Lead the development of next-generation memory interfaces and evaluate high-speed interface IP.
• Manage post-silicon validation and qualification of high-speed interfaces for New Product Introduction.
• Partner with chip/system design teams and external vendors to define SI/PI design goals.
• Develop innovative methodologies to enhance simulation accuracy and productivity.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.