The ASIC Design Verification Engineer role at Google focuses on shaping the future of AI and ML hardware acceleration through the development of cutting-edge TPU technology. This position is part of a team dedicated to creating custom silicon solutions that enhance Google's AI/ML applications. The engineer will leverage their expertise in design verification to ensure the functionality and performance of complex digital designs, particularly in TPU architecture. This role involves collaboration with design engineers and contributes to the innovation behind products used by millions worldwide.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience with design verification.
• Experience in verifying digital logic at RTL using SystemVerilog/UVM for ASICs.
• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science is preferred.
• 6 years of experience with industry standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips.

• Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
• Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM).
• Identify and write all types of coverage measures for stimulus and corner-cases.
• Debug tests with design engineers to deliver functionally correct design blocks.
• Close coverage measures to identify verification holes and to show progress towards tape-out.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.