The TPU RTL Design Engineer will work on shaping the future of AI/ML hardware acceleration by developing custom silicon solutions for Google's Tensor Processing Units (TPUs). This role involves collaborating with cross-functional teams to create innovative and efficient hardware solutions that power Google's most demanding AI/ML applications. The engineer will leverage expertise in digital logic design and RTL coding to contribute to the microarchitecture and implementation of key digital logic blocks. This position offers the opportunity to manage technical challenges in a dynamic and collaborative environment.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 2 years of experience with RTL Design.
• Experience with digital design, including synchronous and asynchronous logic, state machines, and bus protocols.
• Experience optimizing designs for performance, power or area.
• Experience collaborating cross-functionally with DV teams on test plan creation and execution.

• Define and document the microarchitecture for digital designs within the TPU.
• Develop high-quality, performant, and power-efficient Register Transfer Level (RTL) code, primarily in SystemVerilog.
• Collaborate with the verification team to develop test plans, debug RTL, and ensure functional correctness.
• Co-ordinate with the physical design team to meet timing, area, power, and manufacturability requirements.
• Contribute to the development and enhancement of design tools, flows, and methodologies.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.