The RTL Design Engineer for TPU Compute at Google will play a crucial role in shaping the future of AI and ML hardware acceleration. This position involves working with cutting-edge TPU technology that powers Google's most demanding applications. The engineer will contribute to the development of custom silicon solutions and collaborate with various teams to ensure the integration of TPU architecture within AI/ML-driven systems. The role emphasizes innovation and the application of computer architecture principles to solve complex problems.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience with digital design using SystemVerilog RTL.
• Experience with Computer Architecture.
• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science is preferred.
• 3 years of digital design experience using SystemVerilog RTL is preferred.

• Create and review Compute subsystem's design microarchitecture specifications.
• Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
• Work with design validation teams to create test plans to verify and debug design RTL.
• Collaborate with physical design teams to ensure design meets physical requirements and timing closure.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.