The IP DFT Engineer role at Google focuses on shaping the future of AI/ML hardware acceleration through the development of custom silicon solutions. You will work within a team that drives cutting-edge TPU technology, contributing to the innovation behind products used by millions. This position involves defining and implementing design-for-test methodologies for digital or mixed-signal chips. You will collaborate with design and physical design teams to ensure high-quality test integration.

• Bachelor's degree in Electrical Engineering, a related technical field, or equivalent practical experience.
• 1 year of experience in DFT architecture, implementation, automatic test pattern generation (ATPG), and verification for SoCs.
• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience is preferred.
• Experience with industry-standard test methodologies and platforms such as ATE, MBIST, JTAG, or System Level Test (SLT) is preferred.

• Complete Test Design Rule Checks (TDRC) and design changes to fix violations to achieve test quality.
• Drive design and integration of DFT logic in Test Chips including IEEE1149.1 TAP controller, Boundary Scan, scan chains, MBIST, Clock Control block, and other DFT IP blocks.
• Insert and connect MBIST logic, including test collars around memories, MBIST controllers, and electronic fuse (eFuse) logic, to core and Test Access Port (TAP) interfaces.
• Design Verification of DFT logic and test pattern generation.
• Develop DFT timing constraints in Synopsys Design Constraints (SDC) for DFT logic.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.