The RTL Design Engineer will work on shaping the future of AI/ML hardware acceleration, specifically focusing on TPU technology that supports Google's demanding applications. This role is part of the AI and Infrastructure team, which is dedicated to delivering breakthrough capabilities and insights at scale. The engineer will leverage their expertise in design and verification to ensure the quality of complex digital designs. This position offers the opportunity to contribute to innovative products that impact millions of users worldwide.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience in ASIC design, design automation, or a related field.
• Experience programming in Python and shell scripting, and experience with SystemVerilog or other hardware description languages.
• Experience with EDA tools and typical ASIC design and verification flows.
• Experience with version control systems such as Git or Perforce and with build systems like Bazel or Make.
• Experience with continuous integration systems such as Jenkins.

• Own Compute IP releases to the SoC and enhance scripts and flows for SoC releases to reduce manual effort and cycle time.
• Use Python to improve efficiency and quality in top-level IP assembly, focusing on connectivity and configuration.
• Automate IP versioning and integration for cross-project consistency.
• Liaise between Design and Physical Design teams to refine automation for reliable, high-quality branch handoffs.
• Partner with multi-functional teams to deploy automation for development pain points and document methodologies.
• Maintain automated systems to validate tool flows and design health.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.