The Senior ASIC Design Engineer role at Google Cloud focuses on shaping the future of AI/ML hardware acceleration, specifically through the development of custom silicon solutions for Tensor Processing Units (TPUs). The position involves collaborating with cross-functional teams to design high-performance subsystems and manage the complete RTL life-cycle. This role offers a unique opportunity to work on innovative projects that impact millions of users worldwide. The engineer will contribute to the foundational infrastructure that powers Google's data center accelerators.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture is preferred.
• Experience with three or more SoC projects/cycles.
• Familiarity with the full ASIC flow, SerDes behavior, and scripting in Python, Tcl, or Perl.

• Drive the complete RTL life-cycle from initial microarchitecture, coding, and documentation to sign-off readiness for high-performance designs.
• Collaborate with system architects to align on chip-level bandwidth, latency, and power objectives.
• Partner with the Verification and Physical Design teams to define test plans and achieve timing closure.
• Identify test requirements, define methodology/tools, and execute testing of silicon systems.
• Develop and maintain policies, processes, procedures, methods, and documentation for silicon deliverables.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.