The Senior TPU RTL Design Engineer will work on shaping the future of AI and ML hardware acceleration by designing custom silicon solutions for Google's Tensor Processing Units (TPUs). This role is part of the inter-chip interconnect team, focusing on high-speed interconnect subsystems for AI and networking accelerators. The engineer will leverage their expertise in ASIC design to contribute to the innovation behind products that power Google's most demanding applications. The position involves collaboration with various teams to ensure the successful implementation of complex digital designs.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 5 years of experience in high-performance ASIC design.
• Experience architecting or designing RTL solutions for digital systems.
• Experience with high-speed interconnects.
• Experience developing networking IP across one or more layers, such as the media access control (MAC), link (L2), or physical (PHY) layers.

• Lead the microarchitecture and RTL execution to deliver high-performance network design components that meet strict power, performance, and area goals.
• Collaborate with system architects and software/firmware teams to ensure alignment between system and IP requirements.
• Own the complete RTL lifecycle from initial microarchitecture, coding, and documentation to ensuring sign-off readiness for Lint, CDC, and synthesis.
• Collaborate with the Verification team to develop test plans, debug RTL, and ensure functional correctness.
• Work closely with the Physical Design team to meet timing, area, power, and manufacturability requirements.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.