The logic library vertical lead will focus on optimizing standard cell libraries for Intel's advanced process nodes. This role involves direct interaction with Intel's foundry customers to identify technology gaps and drive co-optimization efforts. The team is part of the Advanced Design & Foundational IP organization, which emphasizes design-technology co-optimization and foundational IP development. The position requires collaboration with physical design engineers and EDA partners to enhance cell performance, power, and area.

• Strong technical understanding of advanced semiconductor technology
• Strong technical understanding of foundation IP design and design-technology co-optimization
• Experience in standard cell library design with a good understanding of MOSFET electrical characteristics
• Experience with library cell characterization methodology and tools and Spice circuit simulations
• Experience in the semiconductor foundry ecosystem from foundry, EDA/IP, or foundry customer perspective
• Excellent oral and written communication skills
• Collaborative mindset and great team player
• Good track record of technical leadership and delivery

• Drive optimization of standard cell libraries to meet internal and external foundry customer needs.
• Interface with key Intel foundry customers to understand technology and library gaps.
• Collaborate with Intel foundry technology development teams and EDA partners for co-optimization.
• Optimize library circuits in close collaboration with physical design engineers.
• Provide optimally tuned layout to improve cell performance, power, and area.
• Collaborate with EDA partners to enhance cell content in the standard cell library.

• Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.