JobsCollateral Design and DFM Engineer
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Collateral Design and DFM Engineer

Intel

Location

Santa Clara, CA, Phoenix, AZ, Hillsboro, OR

Type

Full-time

Posted

6/5/2026

Compensation

$190,650 - $269,150 per year

PhD with 5+ Years of Experience
Approval 96.6%·Filings 2,117·New hires 632·
💎 Strong Sponsor
·FY 2025

Job description

The Collateral - Design and DFM Lead Engineer will play a crucial role in advancing high-volume manufacturing and ramping leading-edge logic technologies. This position is part of Intel's Manufacturing Development and Customer Engineering team, which focuses on enhancing design for manufacturability methodologies to improve performance and yield across a diverse product portfolio. The engineer will collaborate with cross-functional teams to define and refine DFM rules and methodologies, ensuring efficient design processes. The ideal candidate will have extensive experience in semiconductor foundry environments and a strong understanding of design and manufacturing constraints.

Requirements

  • Master or Ph.D. degree in Electrical Engineering, Physics, or related field with 10+ years of experience in DTCO and/or DFM within semiconductor foundry or advanced technology development environment.
  • Strong understanding of DTCO skills including SRAM, Standard cells, Process Integration, Yield, and Device.
  • Experience in leading cross functional groups in defining derivative architectures including Design rules, transistors and interconnects.
  • Proven track record in foundry environment developing and implementing DFM solutions for varied customer requirements across multiple market segments.
  • Hands-on experience in advanced node test chip design and scribe line optimization for 3nm-16nm FinFETs and sub 3nm GAA FETs.

Responsibilities

  • Lead cross functional teams across process integration, device, yield, design, OPC, RET, DR and DTP/CAD teams to define and enhance Design for Manufacturability rules.
  • Enhance and feed silicon learning and sighting of yield issues for design teams to update layout and DTCO methodologies.
  • Work and refine yield tools and flows inside the foundry to help in inline yield detection and optimization.
  • Define and refine DFM methodologies by understanding silicon process flows and predicting rules for avoiding layout and design marginalities.

Benefits

  • Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.

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