The TPU RTL Design Engineer will work on shaping the future of AI/ML hardware acceleration by developing custom silicon solutions for Google's Tensor Processing Units (TPUs). This role is part of the inter-chip interconnect team, focusing on designing ASIC/SoC hardware for AI and networking accelerators. The engineer will engage in project definition, RTL design, and implementation, contributing to the innovation behind Google's AI-driven products. This position offers the opportunity to solve challenging technical problems in a collaborative environment.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience in high-performance ASIC design.
• Experience architecting or designing RTL solutions for digital systems.
• Experience developing networking IP across one or more layers, such as the media access control (MAC), link (L2), or physical (PHY) layers.
• Experience with high-speed interconnects.

• Collaborate with the Verification team to develop test plans, debug RTL, and ensure functional correctness.
• Work closely with the Physical Design team to meet timing, area, power, and manufacturability requirements.
• Define and document the microarchitecture for complex digital designs within the TPU.
• Write high-quality, performant, and power-efficient RTL code, primarily in SystemVerilog.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.