Intel is seeking a Logic Design Engineer for its multiprotocol SerDes design team in Santa Clara. This role focuses on high-speed SerDes design, requiring expertise in logic design, RTL coding, and simulation. The engineer will work closely with a multi-national team to ensure the successful integration and verification of IP blocks. The position offers an opportunity to contribute to next-generation products and drive quality assurance compliance.

• Bachelor's degree in Electrical/Computer Engineering and 8+ years of experience or a Master's degree with 6+ years of industry experience.
• Minimum 5+ years of experience in mixed signal design specifically in high-speed SerDes design and architecture.
• Detailed knowledge of SerDes PMA and PCS layers.
• Experience with post-silicon validation and support of the high-speed SerDes IP.
• Ability to read and interpret technical specs to develop microarchitecture and implement RTL design in System Verilog.
• Familiarity with computer system architecture and digital design.
• Experience with OVM/UVM methodology for validation content development.

• Perform logic design of high-speed SerDes, including RTL coding and simulation for IP generation.
• Participate in defining architecture and microarchitecture features of the design block.
• Apply strategies and tools to write RTL and optimize logic to meet power, performance, area, and timing goals.
• Review verification plans and implementations to ensure design features are correctly verified.
• Support SoC customers to ensure high-quality integration and verification of the IP block.
• Drive quality assurance compliance for smooth IP SoC handoff.

• Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.