Senior SoC Compute/Memory Subsystem Architect
IntelSenior SoC Compute/Memory Subsystem Architect
IntelLocation
Santa Clara, CA, Fort Collins, CO, Folsom, CA, Austin, TX, Phoenix, AZ, San Jose, CA
Type
Full-time
Posted
6/11/2026
Compensation
$164,470 - $269,100 per year
Job description
The Senior SoC Compute/Memory Subsystem Architect role at Intel's CEG NAG team focuses on defining the architecture for high-performance networking silicon. This position involves optimizing compute complexes and memory subsystems for next-generation IPU/DPU platforms. The architect will work on system-level performance, scalability, and power efficiency while ensuring seamless integration with networking and storage subsystems. The role requires collaboration across various engineering disciplines to drive architecture alignment and resolve trade-offs.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a STEM related field.
- 7+ years of experience in SoC, CPU, or memory subsystem architecture.
- Experience with CPU architecture and cache hierarchies.
- Knowledge of memory subsystems including DDR/HBM and controllers.
- Familiarity with coherent and non-coherent interconnect architectures.
- Experience in system-level performance and PPA trade-off analysis.
- Ability to drive architecture definition from concept to silicon.
Responsibilities
- Define architecture for IPU compute complexes including core selection and scaling strategy.
- Architect compute subsystem roles such as control plane and data plane assist.
- Drive compute architecture decisions balancing performance, power, and area.
- Define and evolve multi-level cache hierarchy and architect coherency models.
- Architect system memory subsystems including DDR/LPDDR interfaces and memory controllers.
- Ensure optimal balance between latency-sensitive control workloads and bandwidth-intensive datapath workloads.
- Define architecture for SMMU/IOMMU supporting virtualization-heavy IPU workloads.
- Architect integration between compute, network, and storage subsystems.
- Define compute and memory strategies for power efficiency and scalability.
- Lead long-term roadmap for compute and memory evolution across IPU/DPU product generations.
- Collaborate with cross-functional teams to drive architecture alignment.
Benefits
- Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.
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