As a Design Verification Engineer on the Wireless SOC team, you will verify complex SOCs and craft reusable UVM Testbenches. This role involves collaborating with various product development groups to enhance wireless systems and improve customer experiences. You will gain insights into large-scale SOC architectures, wireless protocols, and multi-chip SOC debug architecture. The position emphasizes pre-silicon RTL verification and requires strong problem-solving skills.

• Minimum requirement of a bachelor's degree
• Experience with System Verilog, Verilog or UVM
• Strong problem solving and analytical skills
• Expertise in SystemVerilog coding and UVM methodology
• Dedicated/hands-on ASIC & SOC DV experience
• Experience with Formal Verification
• Low Power Verification experience

• Verify complex SOCs and integrate sophisticated IP level DV environments.
• Craft highly reusable best-in-class UVM Testbenches.
• Implement effective coverage driven and directed test cases.
• Deploy new AI tools and methodologies to improve quality of tape-out readiness.
• Collaborate with other product development groups to push industry boundaries.

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.