As a Design Verification Engineer on the Wireless SOC team, you will verify complex SOCs that are integral to the latest iPhones. This role involves crafting reusable UVM Testbenches and implementing methodologies to enhance tape-out readiness. You will collaborate with various product development groups to push the boundaries of wireless systems and improve customer experiences. The position offers a chance to learn about SOC architectures, wireless protocols, and multi-chip SOC debug architecture.

• Minimum requirement of a bachelor's degree
• Experience with System Verilog, Verilog or UVM
• Strong problem solving and analytical skills
• Expertise in SystemVerilog coding and UVM methodology
• Dedicated/hands-on ASIC & SOC DV experience
• Experience with Formal Verification
• Low Power Verification experience

• Pre-silicon RTL verification of block and top-level SOC.
• Craft and productize state of the art Wireless SOCs.
• Implement effective coverage driven and directed test cases.
• Deploy new AI tools to improve verification processes.
• Collaborate with cross-functional teams to meet complex Wireless protocol chip requirements.

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.