The RTL Design and Integration Engineer role at Google focuses on shaping the future of AI/ML hardware acceleration, specifically through the development of Tensor Processing Units (TPUs). The position involves collaboration with cross-functional teams to design and integrate key digital logic blocks within the TPU architecture. The engineer will leverage their expertise in digital logic design and RTL coding to create efficient hardware solutions. This role is critical in driving innovation and ensuring the performance of Google's AI applications.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 1 year of experience in RTL design.
• Experience with digital design and microarchitecture design.
• Cross-functional experience with DV and PD teams.

• Define and document the microarchitecture for digital designs within the TPU.
• Write high-quality, performant, and power-efficient Register Transfer Level (RTL) code, primarily in SystemVerilog.
• Collaborate with partner teams to support integration efforts.
• Collaborate with the Verification team to develop test plans, debug RTL, and ensure functional correctness.
• Support post-silicon validation and debug efforts.
• Work closely with the Physical Design team to meet timing, area, power, and manufacturability requirements.
• Contribute to the development and enhancement of design tools, flows, and methodologies.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.