The Senior SoC Chiplet Architect role at Intel's CEG NAG team focuses on defining the architecture strategy for multi-generation, chiplet-based SoC platforms aimed at next-generation data center workloads. This position involves driving modular and scalable SoC design approaches while ensuring high performance and efficiency in networking solutions. The architect will lead studies on chiplet partitioning, die-to-die interconnect architecture, and system-level tradeoff analysis. The role requires collaboration across various teams to align on architectural decisions and drive innovation in high-performance networking silicon.

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a STEM-related field.
• 7+ years of experience in SoC/system architecture, including end-to-end architecture definition from requirements to silicon execution.
• Experience with multi-die/chiplet partitioning and the associated system implications.
• Ability to run architecture trade-off studies and communicate decisions to senior technical and business stakeholders.

• Define the monolithic vs. chiplet decision framework and multi-generation roadmap.
• Lead architecture studies for multi-chiplet scaling, including partition boundaries and SKU scalability.
• Drive functional partitioning across chiplets while balancing performance, power, and validation complexity.
• Architect die-to-die communication for high bandwidth and low latency across chiplets.
• Define coordinated power delivery and power management flows across chiplets.
• Lead quantitative trade studies across performance, power, area, cost, and schedule.
• Drive alignment across architecture, RTL, DV, FW/SW, packaging, and platform teams.

• Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.