The Qualcomm Memory Design/Technology Team is seeking a candidate to focus on System PDN and power modeling for high-performance chips. The role involves optimizing PDN architecture to ensure robust performance and low noise in computing applications. Candidates will work across various teams to develop solutions that meet reliability and performance requirements. This position offers a unique opportunity to contribute to cutting-edge technologies in edge AI and connected computing.

• Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design experience, or a Master's degree with 7+ years, or a PhD with 6+ years.
• Experience in PDN, optimal decoupling capacitance placement, and power modeling.
• Good knowledge of signal and power integrity, and chiplets.
• Proficiency in the use of EDA tools such as Voltus, Redhawk, SPICE, and Virtuoso.
• Familiarity with programming languages such as C/C++/Python or scripting languages like Perl/Python.

• Develop and optimize PDN memory and computing architectures for high density and performance.
• Develop and validate models for power and power density under different workloads.
• Identify critical power scenarios and provide solutions within packaging and floorplan constraints.
• Simulate and emulate system power behavior across various power scenarios.
• Identify locations of power switches and utilize optimal control mechanisms.

• Qualcomm offers competitive compensation, annual bonuses, stock programs, comprehensive healthcare coverage, retirement plans, wellness programs, parental leave, flexible work options, and professional development opportunities.