JobsDigital ASIC Design Engineer for Mixed-Signal IPs
Digital ASIC Design Engineer for Mixed-Signal IPs
QualcommDigital ASIC Design Engineer for Mixed-Signal IPs
QualcommLocation
San Diego, CA
Type
Full-time
Posted
6/11/2026
Compensation
$115,600 - $173,400 per year
Master's with 2+ Years of Experience
Approval 97.1%·Filings 1,170·New hires 255·
✓ Established Sponsor
·FY 2025Job description
The Mixed-Signal IP team at Qualcomm is looking for skilled RTL and ASIC design engineers to develop next-generation Mixed-Signal IPs, including DAC, ADC, and PLLs. This role involves collaboration with cross-functional teams to architect, design, implement, and validate complex IP blocks. Engineers will support multiple business units and must understand the full ASIC design flow and advanced semiconductor technologies. The position offers an opportunity to work on innovative projects that are integral to Qualcomm's product portfolio.
Requirements
- Master's degree in Electrical Engineering, Computer Engineering, or a related field
- 3+ years of experience in RTL and ASIC design
- Proficiency with industry-standard front-end ASIC design tools including VCS, Fusion Compiler, PrimeTime, Power Compiler, DFT Compiler, and Spyglass
- Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience, OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience, OR PhD in Science, Engineering, or related field
Responsibilities
- Architect and define the digital design of Mixed-Signal IPs in collaboration with system architecture and analog design teams
- Develop micro-architecture and implement RTL for complex mixed-signal IP blocks
- Apply advanced techniques in computer architecture, digital signal processing, and ASIC design to enhance power, performance, and area
- Utilize industry-standard ASIC design tools for lint checking, clock domain crossing analysis, design-for-test, synthesis, formal verification, and static timing analysis
- Design and analyze DFT logic, including ATPG for stuck-at fault and transition delay fault coverage
- Create comprehensive design documentation, including hardware specifications
- Collaborate with the design verification team to define test plans, verify designs, and fix bugs
- Work with the physical design team to support floorplanning, placement, and timing closure of IPs
- Support SoC integration and debug, including pre-silicon simulation and post-silicon bring-up
Benefits
- Qualcomm offers competitive compensation, annual bonuses, stock programs, comprehensive healthcare coverage, retirement plans, wellness programs, parental leave, flexible work options, and professional development opportunities.
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