Qualcomm is seeking a CPU Physical Design expert to enhance performance, power efficiency, and scalability in next-generation CPU designs. This role involves working on advanced CPU cores and addressing complex challenges in semiconductor design. The position offers significant visibility and influence over architecture and implementation strategies. The ideal candidate will have extensive experience in ASIC/SoC Physical Design and will mentor junior engineers while contributing to innovative design methodologies.

• 10+ years of experience in ASIC/SoC Physical Design
• Strong experience with full RTL-to-GDSII implementation including synthesis, place & route, STA, and signoff
• Experience in timing closure and power optimization
• Scripting skills in TCL, Python, or similar

• Own critical portions of CPU implementation from RTL to GDS with a focus on PPA convergence and design quality
• Drive timing, power, and area optimization for high-frequency, complex CPU subsystems
• Partner with Architecture, RTL, and Circuit teams to co-optimize design for physical implementation
• Solve hard silicon problems such as timing closure, congestion, variability, EM/IR, and power integrity
• Develop and deploy methodologies, flows, and automation to improve scalability and QoR across projects
• Influence and collaborate with EDA vendors and CAD teams to enhance tool capabilities
• Contribute to next-gen design strategies for advanced nodes
• Mentor junior engineers and help raise the technical bar of the team

• Qualcomm offers competitive compensation, annual bonuses, stock programs, comprehensive healthcare coverage, retirement plans, wellness programs, parental leave, flexible work options, and professional development opportunities.