Qualcomm is seeking physical design engineers to join its Digital ASIC Team, focusing on SOC and core design. The role involves innovating and implementing chips and cores using advanced tools and technologies. Engineers will work on high-speed, low power designs and contribute to the complete Physical Design Flow. Candidates should have a strong understanding of various design constraints and be proficient in scripting and software languages.

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design experience, or a Master's degree with 3+ years, or a PhD with 2+ years.
• 2-10+ years of industry experience in Physical Design.
• Experience with Place & Route tools such as Cadence Innovus and/or Synopsys Fusion Compiler.
• Timing closure experience in Synopsys PTSI.
• Experience in formal verification and power domain analysis.

• Innovate, develop, and implement chips and cores using state-of-the-art tools and technologies.
• Manage the complete Physical Design Flow and deliver complex designs.
• Develop low power implementation methods and customized P&R for area reduction.
• Conduct floorplanning, power planning, and IR drop analysis.
• Debug timing violations and implement timing fixes and functional ECOs.

• Qualcomm offers competitive compensation, annual bonuses, stock programs, comprehensive healthcare coverage, retirement plans, wellness programs, parental leave, flexible work options, and professional development opportunities.