The role at Qualcomm Technologies, Inc. focuses on engineering within the ASICS Engineering group, specifically in synthesis and logic equivalence checking (LEC). Candidates will work on physical synthesis methodologies using industry-standard tools and will be involved in timing closure for multi-clock domain designs. The position requires a strong understanding of low-power design implementation and scripting languages. Successful candidates will collaborate with design, DFT, and PD teams to ensure high-quality netlist delivery and timing constraints validation.

• Minimum 0 to 3 years of hands-on experience in synthesis and LEC
• Bachelor's degree in Science, Engineering, or a related field
• Proficiency in Python and Tcl scripting languages
• Familiarity with synthesis tools such as Fusion Compiler or Genus
• Fair knowledge in LEC and low-power signoff tools

• Develop and implement timing constraints for synthesis and timing closure.
• Optimize performance and timing closure at different levels.
• Handle ECOs and formal verification to maintain high quality metrics.
• Collaborate independently with design, DFT, and PD teams for netlist delivery.
• Utilize power optimization techniques such as clock gating.

• Qualcomm offers competitive compensation, annual bonuses, stock programs, comprehensive healthcare coverage, retirement plans, wellness programs, parental leave, flexible work options, and professional development opportunities.