The RTL Design Engineer role at Google focuses on shaping the future of AI/ML hardware acceleration through the development of custom TPU technology. The position involves working on SoC-level RTL design for data center accelerators and requires collaboration with software and system hardware teams. The engineer will contribute to the design and verification of complex digital designs, particularly in the management and control subsystems. This role is part of a team that drives innovation in AI and infrastructure, delivering powerful computing capabilities to Google and its customers.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• Experience with scripting languages.
• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture is preferred.
• 8 years of experience in ASIC design.
• Experience interacting with software, system hardware, and other cross-functional teams.
• Understanding of digital design fundamentals, including synchronous and asynchronous logic, state machines and bus protocols.

• Create and review management and control subsystem's design microarchitecture specifications.
• Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
• Evaluate features and their impact in collaboration with architecture and power teams.
• Create test plans to verify and debug design RTL with design validation teams.
• Ensure design meets physical requirements and timing closure with physical design teams.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.