The Senior SoC Design Engineer role at Google focuses on shaping the future of AI/ML hardware acceleration, specifically through the development of custom silicon solutions for Tensor Processing Units (TPUs). This position is part of a cross-functional team that collaborates with various ASIC development teams to design and implement complex digital designs. The engineer will leverage their expertise in digital logic design and RTL coding to create innovative hardware solutions. This role offers the opportunity to tackle technical challenges at the forefront of AI hardware in a dynamic and collaborative environment.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 5 years of experience with RTL coding using Verilog/SystemVerilog.
• Experience with industry-standard EDA tools for simulation, synthesis, and power analysis.
• Experience with CDC, RDC, RTL Linting and LEC.

• Write high-quality, performant, and power-efficient Register Transfer Level (RTL) code, primarily in SystemVerilog.
• Collaborate with the Verification team to develop test plans, debug RTL, and ensure functional correctness.
• Work closely with the Physical Design team to meet timing, area, power, and manufacturability requirements.
• Engage in CDC and RDC tool setup, analysis, triage and design changes.
• Define and document the microarchitecture for complex digital designs within the TPU.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.