Apple's Silicon Engineering Group is seeking experienced engineers for CPU block-level implementation. The role focuses on driving electrical verification closure and power grid design while collaborating with various teams to ensure design quality and schedule adherence. Candidates will work on innovative solutions in a dynamic environment, contributing to groundbreaking Apple products. This position requires a strong background in silicon level power delivery and VLSI design.

• Minimum BS degree and 10+ years of relevant industry experience
• Experience with silicon level power delivery, electromigration, and IR drop analysis
• Experience with scripting of SAPR or EMIR flow automation
• Experience implementing high-performance and low-power VLSI designs
• Understanding of challenges related to the latest deep sub-micron technology
• Working knowledge of industry standard tools like Apache Redhawk and Cadence Voltus

• Drive block and top-level EMIR/electrical verification closure
• Work on power grid design, construction, and implementation
• Collaborate with CAD/EDA vendors to ensure fidelity of analysis results
• Work with implementation teams to drive design and sign-off closure
• Produce impactful design fixes and automate processes across multiple tool domains
• Regularly summarize the state of the design and drive design convergence across teams

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.