NVIDIA is seeking a Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. This role involves managing the complete custom layout process and collaborating with various teams to ensure high-quality memory IP delivery. The engineer will work closely with circuit design, physical design, integration, CAD, and foundry teams. This position is ideal for an experienced individual contributor who can produce complex layouts and mentor junior engineers.

• Have a BSEE or equivalent experience
• 10+ years of custom IC layout experience, including 5+ years in SRAM, memory compiler, or full-custom memory IP layout
• Hands-on participation in advanced CMOS technology initiatives, preferably concentrating on FinFET or GAA nodes at 5nm, 3nm, or smaller dimensions
• Solid grasp of SRAM and memory layout principles
• Extensive experience in Cadence Virtuoso applied to custom layout creation and assessment
• Extensive experience in DRC/LVS debugging using Calibre, ICV, or similar physical verification tools
• Experience with floorplanning, block-level routing, macro assembly, pin planning, boundary/interface management, and top-level physical verification
• Direct familiarity with advanced-node layout limitations and layout-dependent phenomena
• Ability to work effectively with circuit build, physical build, integration, CAD, and foundry teams
• Clear communication, strong ownership, good judgment, and the ability to mentor other engineers

• Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies
• Develop and improve floorplans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly
• Carry out, debug, and complete DRC, LVS, ERC, antenna, and associated physical verification checks with tools such as Calibre, ICV, or similar workflows
• Support EM/IR review, power integrity, density/fill, DFM, dummy insertion, layout-dependent effects, and other requirements for tapeout
• Collaborate with circuit designers to convert schematics into layouts, ensuring matching, symmetry, shielding, parasitic targets, and reliability constraints are maintained
• Collaborate with PnR and integration teams to resolve top-level DRC/LVS, pin access, boundary, routing, power-grid, and macro-integration issues
• Implement and advance layout methodology, checklists, reusable practices, and quality standards for consistent memory IP delivery
• Collaborate with foundry, CAD, and methodology teams on rule interpretation, deck behavior, waivers, and advanced-node process constraints
• Review layouts, mentor junior engineers, and help raise layout quality and execution rigor across the team

• Employees at NVIDIA are often offered comprehensive, day-one benefits—including medical, dental, and vision coverage with HSA support, life and disability insurance, an Employee Assistance Program, and a 401(k) with auto-enrollment. Many roles also have generous time off and holidays, donation matching (up to $10,000), and a wide menu of extras like FSAs, commuter benefits, legal and identity-theft protection, pet insurance, and wellness discounts. Optional programs can include student-loan and home-purchase support, plus family care resources and expert medical services.