The Senior Physical Design Flow and Methodology Engineer role at Google focuses on shaping the future of AI/ML hardware acceleration through the development of cutting-edge TPU technology. This position involves driving innovations in custom silicon solutions and enhancing physical design methodologies within the Google Compute Engine environment. The engineer will collaborate with chip design teams to streamline workflows and ensure high-quality results for ASIC tapeouts. The role is part of a team dedicated to redefining capabilities in AI and infrastructure.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with physical design flow and methodologies.
• Experience with EDA tools for physical design such as Cadence, Synopsys, or Siemens.
• Experience in full-chip or block-level physical design.
• Experience with scripting in Python, Tcl, or Perl.

• Architect and implement next generation physical design EDA and CAD tool workflows for ASIC development.
• Collaborate with chip design teams to implement tools and methodologies for physical design in leading edge process nodes.
• Develop auditing tools, checkers, and metric dashboards based on APIs from third-party EDA tools.
• Own the physical design of blocks and subsystems end-to-end.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.