The RTL Design Engineer for Digital Signal Processing at Google will play a pivotal role in shaping the future of AI/ML hardware acceleration. This position involves driving the development of cutting-edge TPU technology that powers Google's most demanding applications. The engineer will work within a high-impact team focused on creating custom silicon solutions, transforming complex DSP algorithms into high-performance RTL. The role requires expertise in front-end design flows to deliver hardware that meets the extreme demands of Google's global infrastructure.

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
• 10 years of experience in design for Digital Signal Processing (DSP) or high-speed digital logic.
• Experience in Verilog/SystemVerilog or VHDL.
• Experience with MATLAB, Python, or C++ for algorithmic modeling and verification.

• Lead the RTL design and implementation of high-speed blocks.
• Transform high-level architectural specifications and communication theory models into efficient, bit-exact SystemVerilog/Verilog implementations.
• Perform fixed-point analysis and micro-architectural trade-offs to optimize for area, power, and performance.
• Drive the front-end design flow, including synthesis, Static Timing Analysis (STA), Clock Domain Crossing (CDC), and Logical Equivalency Checking (LEC) to ensure robust, sign-off quality designs.
• Collaborate closely with verification teams to develop bit-exact C++/SystemC models and UVM environments for comprehensive RTL verification.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.