The Senior Test Engineer for CMOS Backplane at Raxium, a part of Google, focuses on developing and optimizing test solutions for microLED display panels. This role involves working closely with design engineers to ensure hardware meets quality and reliability standards. The engineer will also interface with various test equipment and collaborate with engineering teams to implement automated testing solutions. This position is crucial for advancing Raxium's innovative semiconductor materials display technology.

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, Physics, or a specialized field, or equivalent practical experience.
• 4 years of experience with Silicon, CMOS, and IC test development.
• 3 years of experience with Silicon test hardware, software debugging, and data analysis in a Research and Development or manufacturing environment.
• Master's degree or PhD in Electrical Engineering, Computer Engineering, Physics, or a related field is preferred.
• Experience with testing software development, Python, and SQL databases, and familiarity with Linux and Ubuntu.

• Develop, validate, and optimize standards and engineering CMOS Backplane test solutions for microLED display panels.
• Interface with wafer-level probe cards, test equipment, and instrumentation to facilitate CMOS/Silicon testing and characterization.
• Identify, diagnose, and resolve electrical issues during wafer-level testing using digital oscilloscopes and other testing equipment.
• Collaborate with CMOS and panel test engineering teams to define and implement high-speed, automated testing solutions for IC/Silicon/CMOS and microLED displays.
• Work with the Test Engineering team to enhance and develop test frameworks based on requirements from the Reliability Team.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.