The role involves working with the RET DR and Tech Def team at Intel to drive Design and process Technology Co-optimization as well as Design For Yield for semiconductor devices. The team focuses on using advanced lithography manufacturing tools to enable next-generation technologies. Candidates will engage with various semiconductor design teams and maintain a deep understanding of VLSI physical design optimization. The position requires strong problem-solving skills and the ability to collaborate effectively with multiple teams.

• Degree in Engineering, Physical Science, Computer Science, or related fields.
• 3+ years of experience in the semiconductor industry with emphasis on physical design and layout optimization.
• 3+ years of experience working with process design rules or patterning modules.

• Apply strong problem-solving and troubleshooting skills to challenging technical problems.
• Engage with semiconductor design teams and fab patterning teams to develop design rules.
• Maintain a deep understanding of VLSI physical design optimization.
• Research, develop, and implement Resolution Enhancement Techniques for existing and novel process technologies.
• Collaborate with process modules and integration teams to develop Module Target Specs.
• Use predictive modeling, statistics, and machine learning to analyze fab process data.

• Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.