The Qubit Control Physical Design Engineer will focus on driving RTL-to-GDS design convergence while ensuring block-level physical design delivery. This role involves collaboration with internal CAD and PD methodology teams to optimize synthesis and place-and-route tools for cryogenic control design. The engineer will also work closely with custom IP teams to enhance memory macros and library standard cells, contributing to the development of physical design methodologies. The position is part of the Corporate Technology Office at Intel, which aims to develop emerging technologies for future computing systems.

• Bachelor’s, Master’s, or Ph.D. degree with 8+ years of relevant experience.
• Experience with logic design and digital circuits.
• Proficiency in Python, PERL/TCL, Linux/Unix shell, and C.
• Knowledge of low power, high frequency physical design techniques.
• Experience with DFT and DFM flows.

• Drive RTL-to-GDS design convergence through logic synthesis and place-and-route tools.
• Ensure block-level physical design delivery and closure of backend flows.
• Collaborate with internal CAD and PD methodology teams on tool features and optimizations.
• Drive physical implementation through various design processes including timing closure and physical verification.
• Work closely with custom IP teams to define and co-optimize memory macros and library standard cells.

• Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.