The RTL Design Engineer for Machine Learning Accelerators at Google will focus on shaping the future of AI/ML hardware acceleration. This role involves driving the development of custom silicon solutions, particularly related to Tensor Processing Units (TPUs). The engineer will work within a team dedicated to pushing the boundaries of technology, contributing to innovations that power Google's AI applications. The position requires collaboration with software teams to ensure functionality and integration within AI/ML-driven systems.

• Bachelor's degree in electrical engineering, computer engineering, computer science, or a related field, or equivalent practical experience.
• 4 years of experience with custom silicon design, such as SoCs or ASICs.
• Experience with RTL design using Verilog or SystemVerilog.
• Master's degree or PhD in electrical engineering, computer engineering, or computer science is preferred.
• Experience with a scripting language, such as Python or Perl.

• Understand the overall application of the chip and propose improvements in design.
• Design and document one or more blocks of an ASIC, including functionality and timing.
• Collaborate with software teams on functionality, interfaces, and documentation.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.