The Senior RTL Design Engineer role at Google focuses on shaping the future of AI/ML hardware acceleration through the development of custom TPU technology. The position involves working on SoC-level Register-Transfer Level (RTL) design for data center accelerators and requires collaboration with software and system hardware teams. The engineer will leverage their expertise in RTL design to contribute to innovative silicon solutions that power Google's AI applications. This role is highly cross-functional and emphasizes the importance of design and verification expertise in complex digital designs.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience in ASIC design.
• Experience with SystemVerilog/RTL coding.
• Experience with scripting languages such as Tcl, Python, or Perl.

• Create and review management and control subsystem's design microarchitecture specifications.
• Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
• Work with architecture and power teams to evaluate features and their impact.
• Collaborate with design validation teams to create test plans for verifying and debugging design RTL.
• Coordinate with physical design teams to ensure design meets physical requirements and achieves timing closure.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.