The IC Package Design Engineer at Google will be part of a team focused on developing custom silicon solutions for Google's direct-to-consumer products. This role involves designing advanced package substrate designs for Machine Learning chips while collaborating with various engineering teams. The engineer will manage all phases of the design process, ensuring high-performance and manufacturability of the products. This position plays a crucial role in enhancing system performance and optimizing power, performance, and area designs.

• Bachelor's degree in Mechanical Engineering, Material Engineering, Electrical Engineering, Technology, Science, or a related field, or equivalent practical experience.
• 4 years of experience in chip package design/layout using Cadence Allegro Package Designer or Mentor Expedition.
• Experience in chip package substrate layout, optimization, design verification, and design for manufacturability.
• Experience in design automation and scripting.

• Develop physical package substrate design of large form-factor packages for high-performance computers.
• Implement methodology and CAD flow for efficient substrate design and enhanced productivity.
• Manage and drive co-design initiatives across chip, package, and system levels.
• Collaborate closely with signal integrity/power integrity, thermal, and mechanical engineering teams.
• Define and document the requirements for the package substrate design and bill of materials.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.