NVIDIA is seeking a Senior Signal Integrity Engineer to join the Packaging and Systems team. This role focuses on high-speed SerDes channel design, simulation, and correlation for advanced packages and data center platforms. The engineer will work across various domains to develop high-speed interconnect solutions critical for HPC and AI applications. The position offers an opportunity to make a significant impact in a diverse and innovative environment.

• BS, MS, or PhD in Electrical Engineering or equivalent experience
• 8+ years of industry experience in signal integrity, high-speed interconnect design, or related hardware development roles
• Strong background in electromagnetics, transmission line theory, channel modeling, and high-speed serial link behavior
• Proven experience with high-speed SerDes design and analysis for advanced packaging and/or large-scale system applications
• Hands-on experience with industry-standard SI tools such as Ansys HFSS, SIwave, Cadence Sigrity, ADS, HSPICE, or equivalent
• Experience building and using channel models, S-parameters, IBIS-AMI based flows, and time/frequency-domain analysis techniques
• Strong understanding of NRZ and PAM4 signaling, equalization techniques, jitter/noise mechanisms, and end-to-end channel budgets
• Experience with simulation-to-measurement correlation and lab-based model validation using VNA, TDR, and high-speed scope measurements
• Ability to work effectively across cross-functional teams and drive technical decisions in a fast-moving product environment

• Lead signal integrity design and analysis for high-speed SerDes channels across die, package, board, connector, socket, and cable interfaces
• Develop and execute simulation flows for advanced packaging technologies with a focus on channel loss, discontinuities, return path behavior, and crosstalk
• Build and optimize chip-package-board co-simulation methodologies for next-generation HPC and data center systems
• Drive SI modeling and design optimization for package escapes, vias, breakouts, interposers, substrates, sockets, and other critical channel structures
• Perform pre-layout and post-layout signal integrity analysis, create design guidelines, and review layouts to ensure electrical performance targets are met
• Correlate simulation with lab measurements using TDR, VNA, oscilloscope, and related measurement techniques to improve model accuracy and signoff confidence
• Work closely with ASIC, package, board, mechanical, thermal, and validation teams to co-optimize electrical performance across the full product stack
• Support interface bring-up, debug, and margin analysis, and help translate correlation learnings into improved design methods and reusable flows
• Automate analysis, data processing, and visualization to improve productivity and scale SI methodology across multiple programs

• Employees at NVIDIA are often offered comprehensive, day-one benefits—including medical, dental, and vision coverage with HSA support, life and disability insurance, an Employee Assistance Program, and a 401(k) with auto-enrollment. Many roles also have generous time off and holidays, donation matching (up to $10,000), and a wide menu of extras like FSAs, commuter benefits, legal and identity-theft protection, pet insurance, and wellness discounts. Optional programs can include student-loan and home-purchase support, plus family care resources and expert medical services.