The Senior CPU RTL Design Engineer – Power Management role at Intel involves designing and delivering power-efficient, high-performance processors within the CPU Design Team. This position requires deep expertise in low-power CPU/SoC design and emphasizes collaboration with architecture, verification, and physical design teams. The engineer will focus on power management and energy-efficient design, contributing to industry-leading silicon. Ideal candidates will have a strong background in RTL development and power-aware design.

• Bachelor's degree in Electrical/Computer Engineering, Computer Science or related field with 9+ years of relevant experience, or a Master's degree with 7+ years of experience.
• Experience with power management concepts such as DVFS, power states, and budgeting.
• Experience in low-power or power-aware CPU or SoC RTL design.
• Proficiency in RTL development using Verilog or SystemVerilog.
• Understanding of debug and system-level design.

• Define, design, and implement CPU microarchitecture features.
• Develop and deliver RTL for CPU IP blocks.
• Drive power, performance, and area optimization with a focus on power-aware RTL design.
• Design and validate multi-clock domain and CDC solutions.
• Contribute to CPU power management features including dynamic voltage and frequency scaling.
• Debug complex RTL and collaborate with verification teams.
• Partner with SoC integration teams for full-chip delivery.
• Contribute to design methodology improvements and scalability.

• Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.