The TPU Compute RTL Design Engineer role at Google involves developing custom silicon solutions for Google's direct-to-consumer products. This position is part of a team focused on creating ASICs that enhance computation in data centers. The engineer will engage in various aspects of project definition, design, and implementation, contributing to the next generation of hardware experiences. The role emphasizes collaboration with cross-functional teams to ensure optimal performance and efficiency.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with digital design using SystemVerilog RTL.
• Experience with power, performance, and area optimizations.

• Create and review the compute subsystem's design microarchitecture specifications.
• Define compute subsystem integration requirements to the SOC.
• Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
• Work with design validation teams to create test plans to verify and debug design RTL.
• Collaborate with physical design teams to ensure design meets physical requirements and timing closure.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.