As an ASIC Design Verification Engineer at Google, you will play a crucial role in shaping the future of AI/ML hardware acceleration. You will work on cutting-edge TPU technology that powers Google's most demanding applications, contributing to the development of custom silicon solutions. The position involves dynamic responsibilities in project definition, design verification, and silicon bring-up, focusing on the architecture and verification of next-generation data center accelerators. You will be part of a team that empowers Google customers with breakthrough capabilities and insights.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience with design verification.
• Experience with SystemVerilog/Verilog.
• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science is preferred.
• 5 years of experience with industry standard tools, languages and methodologies relevant to the development of silicon-based individual contributors (ICs) and chips.

• Plan the verification of complex digital design blocks by understanding the design specification and interacting with design engineers.
• Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM).
• Identify and write all types of coverage measures for stimulus and corner-cases.
• Debug tests with design engineers to deliver functionally correct design blocks.
• Close coverage measures to identify verification holes and to show progress towards tape-out.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.