The Design Technology Co-Optimization Engineer at Google will work on shaping the future of AI/ML hardware acceleration, specifically focusing on TPU technology. This role involves bridging the gap between process technology and product architecture to define next-generation datacenter-class silicon. The engineer will conduct experiments and analyses to influence design and optimize performance. The position is part of a team dedicated to delivering breakthrough capabilities and insights through advanced computing solutions.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 2 years of experience in Physical Design (RTL-to-GDS) or Technology Development, focusing on advanced nodes.
• Experience in scripting and automation using Tcl and Python (or Perl) to manage design sweeps and data extraction.
• Experience with industry-standard Place and Route (P&R) tools and Static Timing Analysis (STA) tools.
• Experience in CMOS device physics, FinFET/nanosheet architectures, and the impact of layout parasitics on PPA.

• Execute high-fidelity Place and Route (P&R) experiments to evaluate the PPA impact of advanced process features.
• Drive Design Technology Co-Optimization (DTCO) by collaborating with foundries and internal technology teams.
• Quantify process entitlement through systematic benchmarking of logic and memory macros.
• Develop automated physical design methodologies and flows to accelerate technology pathfinding.
• Influence System Technology Co-Optimization (STCO) by partnering with Hardware Architects and Circuit Designers.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.