JobsVerification Engineer Senior
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Verification Engineer Senior

Intel

Location

Austin, TX

Type

Full-time

Posted

6/25/2026

Compensation

$190,610 - $269,100 per year

Undergraduate with 5+ Years of Experience
Master's with 5+ Years of Experience
Approval 96.6%·Filings 2,117·New hires 632·
💎 Strong Sponsor
·FY 2025

Job description

Intel is seeking a highly qualified candidate to join their ASIC design verification team, focusing on next-generation semiconductor product development. The team emphasizes innovative methodologies and efficient execution to drive impactful technology development. Candidates will advance their careers by utilizing cutting-edge verification techniques and leading custom SystemVerilog/UVM development. This role involves mentoring junior engineers and shaping the future of chip development through comprehensive verification strategies.

Requirements

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related STEM field with 8+ years of experience in ASIC/FPGA design verification, or a Master's degree with 6+ years of experience.
  • Strong understanding of object-oriented programming principles and their application in SystemVerilog UVM or other verification methodologies.
  • Experience developing UVM and/or Formal based verification architectures and methodologies.
  • Familiarity with industry standard protocols such as AMBA AXI/AXI-S/CHI and low-speed communication protocols like UART, SPI, I2C/I3C.
  • Strong debugging skills and experience with coverage-driven verification and constrained-random testing.

Responsibilities

  • Define and implement scalable and reusable verification plans, test benches, and verification environments for blocks, subsystems, and SoCs.
  • Create detailed test plans and drive technical reviews with design and architecture teams to validate these plans.
  • Implement and run block/subsystem/cluster/soc simulation models to verify design, analyze power and performance, and identify bugs.
  • Replicate, root cause, and debug issues in the pre-silicon environment, implementing corrective measures for failing tests.
  • Collaborate closely with SoC architects, micro architects, full chip architects, RTL developers, post-silicon, and physical design teams.
  • Continuously improve existing functional verification infrastructure and methodologies.
  • Update test plans based on learnings from post-silicon validation to address missing coverages.
  • Lead and mentor junior engineers, fostering their growth and development in a collaborative environment.

Benefits

  • Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.

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