The ASIC Power Engineer for ML Accelerators at Google will focus on shaping the future of AI/ML hardware acceleration, specifically working on the power efficiency of Tensor Processing Units (TPUs). This role involves collaborating with a team to develop custom silicon solutions that enhance Google's AI/ML applications. The engineer will leverage their expertise in power design and optimization to drive power efficiency goals and contribute to the design and implementation of next-generation data center accelerators. The position is part of a dynamic team that empowers Google customers with advanced capabilities and insights.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience in silicon design or architecture, including logic design, power architecture, performance, or SoC design.
• Experience with power design, power modeling, power architecture, or power reduction methodologies.

• Contribute to design power modeling and drive convergence to power goals.
• Investigate, specify, and deploy architectural and microarchitectural power optimization techniques.
• Define best practices and methodologies to achieve low-power designs.
• Collaborate with cross-functional software and system teams to create novel power management architectures to meet power goals.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.