The entry-level engineer will join Apple's Custom Timing CAD team, which is responsible for transistor-level timing verification and formal verification in custom IC design. This role involves supporting and developing critical sign-off flows using tools like NanoTime and ESP. The engineer will collaborate closely with analog and digital designers to set up flows, debug issues, and ensure clean sign-off. This position offers an opportunity to work at the intersection of circuit design and CAD engineering, contributing to the quality and schedule of advanced chips.

• Minimum of a BS degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 2 years of relevant industry experience.
• Programming or scripting experience in Perl, Python, TCL, or a similar language.
• Foundational understanding of digital or custom IC design and static timing analysis through coursework or internship experience.
• Knowledge of formal verification tools and concepts and experience with SystemVerilog RTL.

• Support and develop flows for transistor-level timing verification and formal verification.
• Partner closely with analog and digital designers across multiple programs and technology nodes.
• Help set up flows, debug issues, and achieve clean sign-off.
• Contribute to the quality and schedule of Apple's most advanced chips.

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.