JobsPrincipal Engineer, Mixed Signal Logic Design Engineer
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Principal Engineer, Mixed Signal Logic Design Engineer

Intel

Location

Folsom, CA, San Jose, CA

Type

Full-time

Posted

6/26/2026

Compensation

$220,920 - $311,890 per year

Undergraduate with 5+ Years of Experience
Approval 96.6%·Filings 2,117·New hires 632·
💎 Strong Sponsor
·FY 2025

Job description

This role involves developing logic design, RTL coding, and simulation for mixed signal and high-speed IPs to create cell libraries and functional units for full chip designs. The position is part of Intel's Central Engineering Group, focusing on customer-driven solutions and measurable business impact. As a principal engineer, the individual will influence technical direction and mentor other technical leaders. The role requires a passion for technology and a proactive approach to complex challenges.

Requirements

  • Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related STEM field with 12+ years of relevant experience, OR proficiency in System Verilog with experience in OVM/UVM methodologies.
  • Demonstrated experience in developing IP or SoC verification environments, writing validation plans, and executing test cases.
  • Master's degree in a related STEM field with 10+ years of relevant experience, OR PhD in a related STEM field with 8 years of experience.
  • 3+ years of experience with DFI/DDR/LPDDR Protocols.
  • Experience in DDR Phy verification or Memory Controller verification.
  • Strong problem-solving skills and a proactive approach to tackling complex technical challenges.
  • Ability to work collaboratively across multidisciplinary teams to achieve technical goals.

Responsibilities

  • Develop the logic design, RTL coding, and simulation for mixed signal and high-speed IPs.
  • Participate in defining architecture and microarchitecture features of the block being designed.
  • Apply strategies, tools, and methods to write RTL and optimize logic to meet design goals.
  • Review the verification plan and implementation to ensure design features are verified correctly.
  • Resolve and implement corrective measures for failing RTL tests to ensure correctness of features.
  • Support SoC customers to ensure high-quality integration of the IP block.
  • Mentor other technical leaders and grow the community within Intel.
  • Align organizational goals with technical vision and formulate technical strategy.

Benefits

  • Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.

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