Intel is seeking an Analog Layout Design Engineer to join their diverse team, focusing on the creation and optimization of complex layouts for analog signal circuits. This role involves collaboration with cross-functional teams to ensure designs meet performance, area, and reliability standards. The engineer will drive innovative layout methodologies and troubleshoot design-related issues. Candidates from all backgrounds are encouraged to apply and contribute to groundbreaking advancements in semiconductor technologies.

• Bachelor's degree or equivalent experience in Electrical Engineering, Computer Engineering, or a related field with 3+ years of experience, or a Master's degree with 2+ years of experience.
• Experience in analog device and metal layout fundamentals, including analog/mixed-signal fundamentals.
• Proficiency in Cadence Virtuoso Layout Suite and Calibre/ICV DRC for design and verification tasks.
• Knowledge of CMOS technologies and high-voltage rules.
• Experience in floor planning and hierarchical layout planning for analog and mixed-signal blocks.

• Design complex layouts of analog signal circuits based on detailed design specifications.
• Conduct a comprehensive set of design verification checks, including process design rules and reliability assessments.
• Develop and analyze floorplans, power grids, ESD structures, and bump layouts to meet performance and electrical requirements.
• Perform floor planning and detailed signal planning for complex analog circuits, ensuring optimization for area, power, reliability, and performance.
• Drive the development and implementation of innovative analog layout methodologies to improve productivity and layout quality.

• Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.