This position is within Intel's Design Technology Platform (DTP) organization, specifically on the PERC ESD development team. The role focuses on developing ESD rule decks for the latest Intel technologies, enabling design teams to accelerate their market readiness. The team is composed of highly motivated engineers tackling complex technical challenges to enhance process design kits (PDKs). The position requires collaboration with various internal and external stakeholders to drive innovation and improve design methodologies.

• Master's degree or PhD in Electrical Engineering or Computer Engineering.
• 3+ years of relevant industry experience in physical design verification.
• 2+ years' experience with ESD PERC rule decks/runset development and debugging.
• 2+ years' experience in scripting for QA and flow automation.

• Develop ESD/LU rule decks aligned with the ESD Design Rule Manual and reliability requirements.
• Create and maintain reliability ESD and LU design rule methodologies and specifications.
• Collaborate with internal design, reliability, and CAD teams as well as external EDA vendors.
• Build and execute test cases for rule debugging, validation, and signoff.
• Define QA requirements and drive related automation to improve robustness and efficiency.
• Lead innovation initiatives to enhance existing ESD/LU verification automation and tools.
• Identify and analyze ESD/LU design problems, define root causes, and drive practical solutions.

• Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.