The SoC DFT Engineer role at Google focuses on shaping the future of AI/ML hardware acceleration, particularly through the development of cutting-edge TPU technology. This position involves defining and implementing advanced design-for-test methodologies for highly digital or mixed-signal chips. The engineer will work closely with the Silicon Engineering team to enhance production quality and reduce test costs. This role is part of a team that drives innovation in AI and infrastructure, delivering powerful computing capabilities to Google services.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 5 years of experience in DFT architecture, implementation, and verification for SoCs.
• Experience in silicon bring-up, debug, or validation of DFT features.
• Experience with industry-standard test methodologies and platforms, such as ATE, MBIST, JTAG, or System Level Test (SLT).

• Develop and document DFT strategy, architecture and test sequences, including hierarchical DFT, MBIST, ATPG and I/JTAG.
• Complete all Test Design Rule Checks (TDRC) and make design changes to fix TDRC violations.
• Develop diagnostic databases, software and hardware for logic and memory fail debug.
• Design and implement system level test strategy.
• Implement core DFT circuitry, including insertion and hook-up of scan chains, DFT compression, Logic BIST, TAP controllers, and Memory BIST (MBIST) logic for IP blocks.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.