JobsSenior Staff Collateral Design and DFM Engineer
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Senior Staff Collateral Design and DFM Engineer

Intel

Location

Santa Clara, CA, Phoenix, AZ, Hillsboro, OR

Type

Full-time

Posted

7/1/2026

Compensation

$161,550 - $317,600 per year

Master's with 5+ Years of Experience
Approval 96.6%·Filings 2,117·New hires 632·
💎 Strong Sponsor
·FY 2025

Job description

The Senior Staff Collateral Design and DFM Engineer will join Intel's Manufacturing Development Customer Engineering team, focusing on high-volume manufacturing and advanced logic technologies. This role involves inventing and enhancing Design for Manufacturability methodologies to improve performance, yield, and ramp speed. The engineer will collaborate with cross-functional teams to define DFM rules and provide actionable feedback for design teams. This position is critical in supporting foundry customers across various market segments.

Requirements

  • Master’s in Electrical Engineering, Physics, or a closely related field
  • 6+ years of experience in DTCO and/or DFM within a semiconductor foundry or advanced technology development environment
  • Experience in DTCO methodologies, including SRAM and Standard Cell design
  • Experience leading cross-functional teams in defining derivative architectures encompassing design rules, transistors, and interconnects
  • Hands-on experience in advanced node test chip design and scribe line optimization across 3nm–16nm FinFET or sub-3nm GAA FET technologies, including Backside Power Delivery (BSPD)

Responsibilities

  • Lead cross-functional teams spanning Process Integration, Device, Yield, Design, OPC/RET, Design Rules, DTP, and CAD to define and enhance DFM rules.
  • Translate silicon learning and yield insights into actionable feedback for design teams.
  • Develop, refine, and optimize yield tools and flows within the foundry environment.
  • Define and evolve DFM methodologies by understanding silicon process flows and collaborating with partners.
  • Drive scribe line layout design and process monitoring structure development.
  • Manage design rule development, validation, and waiver processes.
  • Serve as the key interface between Process Integration, Yield, Device, and Design teams.
  • Support foundry customers by developing and implementing tailored DFM solutions.

Benefits

  • Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.

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