The Physical Low Power Validation Engineer at Google will focus on shaping the future of AI/ML hardware acceleration by driving cutting-edge TPU technology. This role involves validating complex digital designs with a specific emphasis on low power signoff and ensuring the integrity of multi-voltage ASICs. The engineer will work closely with the AI and Infrastructure team to deliver innovative solutions that power Google's AI applications. This position requires a blend of technical expertise and collaboration to bridge the gap between design and execution.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience in post-layout physical netlist validation or low-power signoff in an ASIC design environment.
• Experience in static low-power rule checking tools or debugging signal corruption or structural checks.
• Experience debugging technical issues within the IEEE 1801 UPF framework or the physical gate-level netlist flow.

• Design, deploy, and carry out post-layout low power verification methodologies according to execution schedules and tape-out signoff criteria.
• Validate the implementation of complex multi-voltage design collateral, performing gate-level checks using industry-standard tools.
• Drive the resolution of complex Physical Design and Place and Route anomalies.
• Perform targeted debugging on advanced Clock Tree Synthesis implementations.
• Drive the continuous refinement of power state tables and Unified Power Format scripts.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.