Rivian is seeking a Principal Neural Network Microarchitect to lead the development of its next-generation Neural Network Engine (NNE) microarchitecture. This role requires broad technical expertise and ownership of critical design matters that will shape future products and technologies. The position emphasizes the architecture of the NNE core, focusing on datapath design, scheduling, and performance scalability for production neural network workloads. The successful candidate will work closely with various teams to ensure efficient execution of neural network workloads.

• Deep expertise in computer architecture and hardware microarchitecture, with a strong track record designing complex silicon blocks from concept through production.
• Strong understanding of neural network inference hardware, including datapath design, scheduling, numerical formats, quantization, and performance optimization.
• Experience architecting or optimizing specialized compute engines such as NPUs, AI accelerators, vector/tensor processors, or systolic-array-based architectures.
• Strong knowledge of memory hierarchy and data movement, including SRAM organization, DMA-based transfer models, buffering, bandwidth management, and latency hiding.
• Experience working across hardware and software boundaries, especially with compiler, runtime, or model deployment teams.
• Proven ability to evaluate architectural tradeoffs using modeling, analysis, and empirical workload characterization.
• Excellent communication skills and the ability to influence across architecture, design, verification, physical design, firmware, compiler, and product teams.
• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field.

• Define and evolve the NNE core microarchitecture, including compute datapaths, instruction flow, scheduling strategy, quantization support, and execution efficiency for neural network inference workloads.
• Architect solutions that map effectively onto Rivian’s NNE hardware model, including the processing array, partitioning strategy, and coordination of instruction and data movement across the engine.
• Drive architectural tradeoffs across performance, power, area, utilization, latency, and scalability.
• Lead definition of mechanisms for efficient movement of activations, weights, and outputs through on-chip and off-chip memory pathways and DMA architecture.
• Partner closely with compiler, model, firmware, verification, and SoC teams to ensure neural network workloads are translated into efficient executable flows for the NNE.
• Define architectural requirements for correctness, observability, resiliency, and debuggability, including support for error handling, recovery hooks, and safe execution flows where needed.
• Build performance models, evaluate bottlenecks, and guide decisions with data across representative production workloads.
• Influence long-range NNE direction, establish technical principles, and serve as a key architecture voice across the silicon organization.
• Mentor engineers across architecture and implementation disciplines and raise the technical bar for neural network accelerator design at Rivian.

• Employees at Rivian are often offered comprehensive health, dental, and vision insurance, a 401(k) with company match, ESPP and potential RSU grants, performance bonuses, and generous time off including paid parental and sick leave. Perks can include 24/7 mental-health coaching and therapy, Hinge Health for Anthem enrollees, tuition assistance and professional development, plus on-site food and a wide range of employee discounts on items like computers, mobile phones, home loans, and pet care.