Qualcomm Technologies, Inc. is seeking skilled engineers for its SoC Implementation Team, focusing on timing constraints development, power analysis, and timing closure for premium-tier chips. This role offers an opportunity to work with the Snapdragon implementation team on advanced SoCs in sub-3nm nodes across mobile, AI, and automotive sectors. Candidates should have a strong background in ASIC design and be proficient with relevant tools. The position emphasizes collaboration with design teams to ensure optimal timing performance.

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design experience, or a Master's degree with 3+ years, or a PhD with 2+ years.
• Proficiency with tools such as Primetime and Fishtail/TCM.
• Scripting skills in Tcl, Perl, or Python are desirable.

• Develop constraints for physical power-aware synthesis and timing analysis.
• Collaborate closely with RTL design and physical design teams to identify timing requirements.
• Generate, review, and validate clock domain crossing and design constraints.
• Analyze timing across modes and corners, understanding path pessimism and margins.

• Qualcomm offers competitive compensation, annual bonuses, stock programs, comprehensive healthcare coverage, retirement plans, wellness programs, parental leave, flexible work options, and professional development opportunities.